Senior Silicon CAD Engineer
Core
Coordinate schedules and validate PDK and cell IP collateral with foundry and IP teams; deploy and maintain physical design implementation tool PPA methodologies and signoff settings for advanced process technologies.
Role type
Senior Silicon CAD Engineer
Builds
Physical design implementation flows and signoff environments for advanced process technologies
Domain
Semiconductor manufacturing / Electronic Design Automation (EDA)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
PDK collateral validation, cell IP validation, PPA methodology development, signoff tool configuration, advanced process technology knowledge, Fusion Compiler, Innovus, PrimeTime, StarRC, PrimePower, RedHawk, TCL scripting, Python scripting
Preferred skills
Scripting for data gathering and regression automation
Responsibilities
Coordinate schedules with foundry teams, validate PDK collateral, collaborate with IP teams, deploy and maintain physical design implementation tools, configure signoff tool settings, automate data gathering and regression via scripts, document and present results
Seniority
Senior, hands-on IC
