RTL Intern
Core
Design microarchitecture and implement logic in Verilog for cutting-edge machine learning architectures.
Role type
RTL Intern (Hardware Design)
Builds
RTL blocks for inference-focused AI chips
Domain
Hardware engineering / AI Infrastructure
Deliverable
production ML models
Required skills
Verilog, SystemVerilog, UVM, Python, ASIC/SoC design concepts, high-speed digital logic, verification/testbenches, physical design flows
Preferred skills
Transformer architectures, numerical representations, clocking and reset schemes
Responsibilities
Contribute to RTL block development, participate in full design cycle from microarchitecture to synthesis and timing feedback, write test benches
Seniority
Intern
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