Senior Design Verification Engineer
Core
Senior Design Verification Engineer responsible for ASIC functional verification of high-performance networking chips (Cisco Silicon One) using SystemVerilog/UVM, covering architectural discussions, emulation, and simulation support.
Role type
Senior IC design verification engineer
Builds
Production ASIC chips for major data centers
Domain
Networking hardware / Semiconductor design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, digital logic design verification, pre-silicon debugging, in-lab debugging, verification coverage analysis, DV infrastructure implementation
Preferred skills
Scripting, System integration (AMBA, PCIe, SPI, I2C, JTAG, CPU), Chip driver level software knowledge, Design knowledge
Technologies
SystemVerilog, UVM, Emulation tools, AMBA, PCIe, SPI, I2C, JTAG
Responsibilities
Implement DV infrastructure for block, cluster, and TOP-level environments; Maintain and enhance existing DV environments; Ensure complete verification coverage through code and functional coverage review; Collaborate with architects and designers to ensure verification completeness; Support tests done with emulation; Prepare for post-silicon-validation
Seniority
Senior, hands-on IC
