Senior Methodologist for AIML Enhanced Design/Verification
Core
Develop and execute verification strategies for complex digital designs using AIML (AI/ML) enhanced methodologies to ensure silicon quality from RTL to tapeout.
Role type
Senior IC design/verification methodology engineer (AIML)
Builds
UVM-based testbench environments, verification plans, and automated RTL generation from specs
Domain
Semiconductor design and verification (Digital IC)
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, digital design fundamentals (RTL, timing, synthesis), simulation tools (Synopsys VCS, Cadence Xcelium, Mentor Questa), AIML methods and workflows, agent/skills/API development
Preferred skills
Formal verification, emulation and FPGA prototyping, industry publications in design/verification methodology
Technologies
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Mentor Questa, JasperGold, VC Formal, Palladium, Protium, Veloce
Responsibilities
Architect and maintain AIML enhanced design/verification infrastructures; create UVM testbenches and verification plans; automate RTL generation from specifications; perform root cause analysis of failures; evaluate industry tools
Seniority
Senior, hands-on IC
