Senior Methodologist for AIML Enhanced Design/Verification
Core
Develop and execute comprehensive verification strategies for complex digital designs using AIML (AI/ML) enhanced methodologies to ensure silicon quality from RTL to tapeout.
Role type
Senior IC Design/Verification Methodology Engineer (AIML)
Builds
UVM-based testbench environments, verification plans, and automated RTL generation from specifications.
Domain
Semiconductor / Digital Design / AI/ML
Deliverable
production ML models
Required skills
AIML methods and workflows, agent and skills architecture, SystemVerilog, UVM, digital design fundamentals (RTL, timing, synthesis), simulation tools (Synopsys VCS, Cadence Xcelium, Mentor Questa)
Preferred skills
Formal verification, emulation and FPGA prototyping, industry publications
Technologies
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Mentor Questa, JasperGold, VC Formal, Palladium, Protium, Veloce
Responsibilities
Architect and maintain AIML enhanced design/verification infrastructures; create UVM testbenches and verification plans; automate RTL generation from specs; perform root cause analysis of failures; evaluate industry tools.
Seniority
Senior, hands-on IC
