Senior ASIC Verification Engineer
Core
Lead VLSI design verification for complex integrated circuits, developing test plans, functional models, and test benches to ensure full functionality of modules and chips.
Role type
Senior IC ASIC verification engineer (VLSI)
Builds
Production-ready VLSI prototypes and chips
Domain
Semiconductor / Hardware / VLSI
Required skills
System Verilog, UVM, constrained-random verification, formal verification, gate simulation, code coverage analysis, C/C++, Perl, Python, VLSI architecture, digital logic, EDA tools
Preferred skills
Machine learning, networking protocols, FPGA tools, patent/publications in VLSI
Technologies
System Verilog, UVM, C, C++, Perl, Python, EDA tools, formal verification tools
Responsibilities
Develop detailed test plans and functional models for VLSI modules; build module-level test benches using System Verilog/UVM; write tests to verify module functionality; collaborate with logic designers and SW engineers to resolve bugs; perform full-chip/sub-system emulation testing; mentor interns and new graduates; drive VLSI innovation and integration of new technologies.
Seniority
Senior, hands-on IC with team leadership
