Principal Engineer, Design Verification Engineering
Core
Lead end-to-end design verification for complex digital SoCs, microprocessor-based designs, AI/ML accelerators, and high-speed peripherals, driving execution from planning to signoff.
Role type
Principal IC Design Verification Engineer (SoC/Subsystem)
Builds
Next-generation Intelligent Edge products including integrated circuits, software, and subsystems leveraging high-performance analog, mixed-signal, and digital signal processing technologies.
Domain
Semiconductor / Digital Design Verification / SoC Architecture
Deliverable
production ML models | product features
Required skills
SoC/Subsystem architecture, Verilog/SystemVerilog, UVM-based testbench development, functional and code coverage closure, NoC/interconnect verification, power-aware verification (UPF), formal verification, high-speed/low-speed interface protocols (I2C, SPI, Ethernet, AXI/AHB, DMA), constrained-random verification, assertions, transaction-level modeling, C/C++, SystemC, Python/TCL/Shell scripting
Preferred skills
Mixed-signal/analog verification (ADC/DAC/PLL/PHY), processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerator verification, security and safety verification, gate-level simulation with timing annotation (GLS)
Technologies
UVM, SystemVerilog, Verilog, Python, TCL, Shell, SystemC, C++, ARM, RISC-V, Tensilica, UPF, GLS
Responsibilities
Lead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff; Verify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies; Define and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance; Collaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies; Drive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early; Architect and implement scalable UVM-based testbenches, DV flows, and methodologies
Seniority
Principal, hands-on IC with leadership
