ASIC Senior Test Engineer, Annapurna Silicon Operations
Core
Develop and debug hardware test solutions for advanced machine learning accelerator silicon, focusing on yield improvement and mission profile testing.
Role type
Senior IC ASIC test engineer (hardware development & debug)
Builds
Test hardware (ATE/SLT/SDP), test suites, and server-level test code for ML accelerator chips. (via careerplan.io/jobs/10570118-asic-senior-test-engineer-annapurna-silicon-operations-at-amazon)
Domain
Semiconductor hardware testing / Machine Learning Infrastructure
Required skills
ATE platform expertise (Advantest 93K, Teradyne IGXL), C/C++ programming, hardware development, yield debugging, OSAT coordination, test collateral creation, system-level test design.
Preferred skills
Lua/Python/shell scripting, multiplatform code porting, test data management (JMP, Optimal Plus, eXensio), FPGA/HBM interface experience.
Technologies
Advantest 93K, Teradyne IGXL, FPGAs, HBMs, JMP, Optimal Plus, eXensio, C/C++, Lua, Python, Shell.
Responsibilities
Develop new ATE/SLT/SDP hardware and test suites; debug yield issues (thermal, contact, power delivery); coordinate OSAT test cell qualification; correlate System-SLT-ATE results; port server testing code from ATE; analyze RMA data to close test coverage gaps.
Seniority
Mid-career, hands-on IC