Sr. PD Methodology Engineer, Annapurna Labs - Cloud Scale Machine Learning
Core
Design and optimize hardware methodologies for custom ML accelerator chips (AWS Inferentia, Trainium) in advanced nodes to enable cloud-scale machine learning.
Role type
Senior IC ASIC Physical Design Methodology Engineer
Builds
Custom ML inference and training datacenter servers
Domain
Semiconductor / Cloud Infrastructure / Machine Learning
Deliverable
production ML models
Required skills
ASIC physical design, RTL-to-GDS flow, CAD flow optimization, EDA tool evaluation, scripting (TCL, Python), dashboard/reporting, digital design, analog/RF layout, verification, automation frameworks, emulation, UVM, C, System C, power island design, wireless protocols (OFDMA, TDMA, CDMA), serial protocols (SPI, I2C, I3C, UART), embedded C, communication theory, OFDM, MIMO, RF engineering, cellular standards (4G/5G, WiMAX, 802.11ad), modem L1/L2 algorithms, link/system simulators, test automation, CI/CD, bare metal environment development
Preferred skills
RTL coding and debug, PPA analysis, modern ASIC/FPGA tools, SOC bring-up, post-silicon validation
Technologies
AWS Inferentia, Trainium, TCL, Python, UVM, MATLAB, C++, Git, CI/CD
Responsibilities
Define and deploy physical design methodologies, drive CAD flow optimizations for PPA/TAT, interface with RTL/Package/DFT teams, troubleshoot digital tool flows, create project tracking dashboards
Seniority
Senior, hands-on IC
