Senior Member Technical Staff
Core
Drive design and development of RTL synthesis technology, logic optimizations, and low power synthesis for complex digital IC designs.
Role type
Senior IC engineer (RTL synthesis & optimization)
Builds
Next generation RTL-to-GDSII solution for chip, board, and system design
Domain
Electronic Design Automation (EDA) / Semiconductor
Deliverable
production ML models | product features
Required skills
C++, algorithm and data structures, RTL synthesis, logic optimizations, low power synthesis
Preferred skills
System Verilog, VHDL, UPF, DFT, formal verification, Dynamic Power, parallel algorithms, Python, Tcl
Technologies
C++, System Verilog, VHDL, UPF, Python, Tcl
Responsibilities
Drive design and development of RTL synthesis technology, logic optimizations, and low power synthesis; Guide and lead others toward successful project completion; Collaborate with a team of experts
