Design Verification Engineer - Interface IP
Core
Design Verification Engineer for Interface IP subsystems ensuring correctness and performance across the hardware-software stack.
Role type
Design Verification Engineer (Interface IP)
Builds
IP subsystems and interfaces for inference-focused AI chips
Domain
Semiconductor / Hardware Design / AI Infrastructure
Deliverable
production ML models
Required skills
SystemVerilog, UVM, PCIe, Ethernet, AXI/AMBA, ARM/ARC CPU protocols, coverage closure, testbench development
Preferred skills
Vendor IP integration, VIP handling, cross-functional collaboration
Technologies
SystemVerilog, UVM, PCIe, Ethernet, AXI, AMBA, ARM, ARC
Responsibilities
Own verification of IP subsystems (PCIe, Ethernet, CPU, peripherals, sensors), develop UVM/SystemVerilog environments, collaborate with integration/SoC DV teams, drive coverage closure and sign-off
Seniority
Mid-Senior, hands-on IC
