Design Lead/ Front-End Architect / Datapath Lead
Core
Define digital front-end micro-architecture and own the high-speed datapath for a first-of-its-kind chiplet, serving as the architectural center connecting UCIe, in-house IP, and the optical engine.
Role type
Founding Front-End Digital Architect / Datapath Lead
Builds
High-throughput chiplet datapath, UCIe streaming interfaces, and optical engine integration blocks
Domain
Photonic AI supercomputing infrastructure, chip-to-chip optical interconnects
Deliverable
production ML models | product features
Required skills
Digital micro-architecture, high-speed datapath design, SystemVerilog RTL, CDC/RDC signoff, UCIe/PCIe/CXL concepts, clocking/reset architecture, design-for-test, physical closure collaboration
Preferred skills
UCIe interface architecture, die-to-die/chiplet experience, FEC/coding datapath, optical transceiver/CPO background, advanced-node design
Technologies
SystemVerilog, UCIe, PCIe, CXL, SVA, UPF
Responsibilities
Define front-end micro-architecture and block partitioning; establish front-end design methodology and quality standards; design high-speed datapath logic and transport framing; collaborate on timing-aware micro-architecture for physical closure; establish designer-level verification and architectural DFT; lead and mentor the front-end design team
Seniority
Founding, hands-on IC with strategic ownership
