Modelling Lead (SystemC / Virtual-Platform Architect)
Core
Build executable SystemC/TLM-2.0 virtual platforms and architecture models for pre-silicon firmware bring-up and design-space exploration for photonic AI supercomputing engines.
Role type
Senior IC SystemC Virtual Platform Architect
Builds
Executable virtual platforms (MCU, peripherals, memory map, UCIe transactor) and architectural performance models for photonic interconnects and AI accelerators.
Domain
Semiconductor hardware design, photonic computing, embedded systems, ESL (Electronic System Level) modeling.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemC, TLM-2.0, modern C++, virtual platform development, architecture modeling, embedded software, hardware micro-architecture, ISS integration, design-space exploration.
Preferred skills
High-speed serial links, chiplet interconnects, UVM/DV verification flow, mixed-signal modeling, control-loop/plant modeling, SerDes systems.
Technologies
SystemC, TLM-2.0, C++, UCIe, Arm ISS, RISC-V, UVM, PCIe, CXL, Ethernet.
Responsibilities
Develop SystemC/TLM-2.0 virtual platforms for pre-RTL firmware execution; create architecture/performance models for latency, throughput, and buffer sizing; build golden reference models for verification teams; model analog/control circuits and integrate third-party ISS; partner with architects and firmware leads to ensure model-RTL-firmware coherence.
Seniority
Senior, hands-on IC
