Host and Network IO FPGA Engineer
Core
Design and implement the full in-chassis IO subsystem for Cerebras' AI chip, connecting distributed server nodes via custom RoCE v2 networks to the WSE.
Role type
Senior IC FPGA engineer (network IO)
Builds
Production-ready bitstreams for large-scale AI inference clusters
Domain
AI hardware / High-performance networking
Deliverable
production ML models | infrastructure
Required skills
Verilog, FPGA placement & routing, timing closure, simulation, debug, RoCE v2 protocol, network switch environments
Preferred skills
AI-augmented development environments, cross-functional technical project leadership
Technologies
Git, Wireshark, Arista, Juniper
Responsibilities
Lead chassis-to-wafer IO architecture and design; Improve current RTL and implement next-gen FPGA designs; Optimize bandwidth/latency over FPGA datapath; Drive network performance debug of large AI clusters; Integrate leading edge networking technologies and protocols.
Seniority
Senior, hands-on IC
