Director- R&D Technical Head
Core
Define and own end-to-end chip design strategy, methodology, and technology roadmap across SoC, Analog, Digital, Product & Test Engineering, Design Packaging, Verification, and DFT verticals.
Role type
Director-level technical head for semiconductor R&D
Builds
Custom SoCs and advanced semiconductor products for global markets
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | infrastructure
Required skills
SoC architecture, Analog design, Digital RTL design, Physical design, Design Packaging, Verification, DFT, EDA toolchains (Cadence, Synopsys), Team management, Project monitoring, Stakeholder communication
Preferred skills
Advanced packaging (2.5D/3D IC, chiplets), AI/ML-assisted EDA flows, Automotive-grade design (AEC-Q100, ISO 26262), Patent generation, Global foundry partnership management
Technologies
Cadence Innovus/Virtuoso, Synopsys Design Compiler/IC Compiler/PrimeTime, TSMC, GlobalFoundries
Responsibilities
Define chip design strategy and technology roadmap, Manage vertical leads and engineering managers, Monitor R&D projects from architecture to tapeout, Present technical risk assessments to senior leadership, Interface with foundry partners and IP vendors, Champion R&D innovation initiatives
Seniority
Director, strategic leadership & large-scale team management
