Sr. Staff NPI Test Engineer
Core
Architect comprehensive test solutions for mixed-signal SiGe products from early silicon validation through high-volume production, enabling next-generation high-speed communication products operating at 200Gbps and beyond.
Role type
Sr. Staff NPI Test Engineer (Strategic IC)
Builds
Reusable test IP, libraries, frameworks, and advanced test methodologies for mixed-signal devices.
Domain
Semiconductor / Mixed-signal / High-speed digital / RF / SiGe BiCMOS
Deliverable
production ML models | product features | infrastructure
Required skills
Advantest V93000 platform (SmarTest 7/8), C/C++/Python/TCL programming, high-speed signal integrity analysis, analog/mixed-signal DFT (BIST, scan, boundary scan), RF/microwave test techniques (>40GHz), statistical process control, PCB design tools (Cadence, Altium), test architecture design, cross-functional technical leadership.
Preferred skills
Master's/PhD in engineering, 8+ years in semiconductor test (SerDes/high-speed I/O), SiGe BiCMOS process technology, automotive quality standards (AEC-Q100), wafer-level testing, probe card design, test data analytics, machine learning for yield enhancement.
Technologies
Advantest V93000, SmarTest 7/8, Cadence, Altium, 93000 PS1600/PS3600, Wave Scale RF.
Responsibilities
Architect test strategies for complex mixed-signal SiGe products from concept to production; lead development of innovative test methodologies for high-speed SerDes and signal conditioning; drive DFT/testability requirements into IC architecture; perform technical risk assessment for test coverage; mentor junior engineers and develop training materials.
Seniority
Sr. Staff, strategic IC with mentorship and architecture authority
