ASIC Design Engineer
Core
Design digital IP blocks for advanced Satellite communication ASICs, supporting reusable space vehicles and TeraWave satellite network.
Role type
ASIC Design Engineer (Digital IP)
Builds
Digital IP blocks for satellite communication ASICs
Domain
Aerospace / Satellite Communications
Deliverable
production ML models | product features
Required skills
RTL design (SystemVerilog/Verilog), digital subsystem fundamentals, microarchitecture definition, PPA tradeoff analysis, cross-functional collaboration
Preferred skills
Space-based communications knowledge, signal processing concepts, radiation-tolerant design, formal verification, high-speed interface design
Technologies
SystemVerilog, Verilog, FPGA
Responsibilities
Support design and delivery of ASIC IP blocks from specification through RTL release; Assist in defining microarchitecture for digital signal-processing and control logic blocks; Participate in design trade studies involving throughput, latency, area, and power; Collaborate with systems, algorithm, and architecture teams to translate requirements into hardware implementations; Work with verification, DFT, physical design, and firmware teams for integration and tape-out readiness; Contribute to RTL development, test plans, and implementation reviews; Support post-silicon bring-up activities and debugging.
Seniority
Junior, entry-level IC
