Software Architect

Cadence

SAN JOSE, US💼 Full-time💰 $185,500–$185,500🗓 2026-09-30 → 2026-10-01

Core

Design, develop, troubleshoot, and support P&R (Place and Route) design flow for digital IC implementation.

Role type

Senior IC design engineer (physical implementation)

Builds

P&R design flow tools and data models for digital ICs

Domain

Semiconductor / Electronic Design Automation (EDA)

Required skills

C/C++, Tcl scripting, hierarchical design flow, database architecture, efficient data access algorithms, UNIX/Linux platforms

Preferred skills

P&R software tool usage, API/Class definition

Responsibilities

Design and develop P&R design flow, enhance data models and databases, optimize performance, debug and support tools

Seniority

Senior, hands-on IC

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About Cadence

Software Development11438San Jose, California, US

Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognize