CareerPlan

Intern Mixed Signal IP

VALBONNE (Sophia), FRInternship2026-10-19 → 2026-11-10
Based in France

Core

Design and benchmark analog and digital circuits to monitor process variations in advanced semiconductor nodes.

Role type

Intern, mixed-signal IP engineer

Builds

Embedded circuits for process variation monitoring

Domain

Semiconductor / Mixed-Signal IP

Required skills

Analog circuit design, Digital circuit design, Semiconductor physics knowledge, EDA tool usage, Circuit benchmarking

Preferred skills

Experience with Cadence Virtuoso, Knowledge of advanced technology nodes

Technologies

Cadence Virtuoso, Mixed-Signal IP

Responsibilities

Review state-of-the-art circuit options for process variation monitoring, Design circuits to track process variations, Benchmark designed circuits

Seniority

Intern