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Product Engineering Architect

SAN JOSE, US💼 Full-time💰 $185,500–$185,500🗓 2026-09-23 → 2026-09-25

Core

Provide senior technical leadership for the development and proliferation of Cadence Virtuoso Heterogeneous Integration technologies, shaping product strategy for physical implementation flows around 3D IC, heterogeneous integration, and advanced packaging.

Role type

Senior IC Product Engineering Architect

Builds

End-to-end solution for system design implementation flows spanning 3D IC, heterogeneous integration, and advanced packaging

Domain

Semiconductor EDA / Physical Implementation / Advanced Packaging

Deliverable

production ML models | product features

Required skills

Semiconductor design expertise, Physical implementation knowledge, Advanced packaging knowledge, Cadence Virtuoso platform mastery, Custom IC design flows, Product strategy definition, Customer requirement synthesis, Technical roadmap planning, Cross-functional leadership, Executive-level communication

Preferred skills

Co-design flows around 3D IC, Heterogeneous integration, Silicon-package-board integration, Cadence Allegro Package Designer Plus (APD+), SKILL language or interpreted languages

Technologies

Cadence Virtuoso, Cadence Allegro Package Designer Plus (APD+), SKILL

Responsibilities

Drive and validate end-to-end solution for system design implementation flows, Lead strategic customer engagements to define advanced methodologies, Influence product roadmap direction by synthesizing market and technical insights, Produce high-quality Product Requirement Specifications (PRS) and technical use cases, Provide technical leadership including requirement trade-off analysis and solution validation, Mentor product engineers on complex design-flow challenges, Create executive-ready technical collateral and enablement materials, Represent product engineering in roadmap discussions and industry events

Seniority

Principal, hands-on IC with strategic influence

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