Principal Design Engineer
Core
Designing, developing, and supporting system-level memory IP models (SDRAM, NAND Flash, eMMC, SD Card, DFI, UFS) for hardware-based verification products.
Role type
Principal Design Engineer (Memory IP & Verification)
Builds
System-level memory IP models and verification products
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/SystemVerilog), RTL verification, complex protocol design, hardware system design, debugging, scheduling and task planning
Preferred skills
Cadence simulation/emulation products, scripting (Perl/TCL/C-shell), memory sub-system design
Technologies
Verilog, SystemVerilog, Cadence simulation tools, Cadence emulation tools
Responsibilities
Schedule, design, develop, and support IP models for system-level memory; update, maintain, and document existing memory model products; perform individual contributor work on RTL design, verification, and productizing; interface with customers on emulation, simulation, or verification problems; collaborate on cross-verification and lifecycle processes
Seniority
Principal, hands-on IC
