RTL2GDS, Senior Principal Design Engineer
Core
Senior Principal Solutions Engineer supporting Chip Designer Customers in achieving superior performance for their Design PPA Goals through RTL-to-GDSII delivery and full flow implementation training.
Role type
Senior Principal Solutions Engineer (Physical Implementation & Methodology)
Builds
Full Flow Implementation Services, competitive benchmarking on complex blocks (CPUs, GPUs, DSP cores), and methodology development for leading-edge technology.
Domain
Semiconductor EDA / Physical Design / ASIC Implementation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical Synthesis, Place and Route (PnR), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Verilog, Low Power Design, Multi-Voltage Design, TCL/Perl Scripting, Design Automation
Preferred skills
Tapeout experience, Multivoltage design implementation, Clock tree debugging, Competitive benchmarking
Technologies
Encounter Digital Implementation Platform, Genus DFT, Encounter Test (ET), Cadence tool portfolio
Responsibilities
Support regional customers and major level customers (50%+ support) in local region; Manage strategic customer evaluations/benchmarks on Cadence front-end solutions; Assist customers with adopting Cadence Front End tools in Synthesis by providing methodology and tool knowledge; Drive best practices and lessons learnt from evaluations back into product development; Create and conduct technical presentations and product demonstrations to customers; Perform methodology assessments and develop new design methodologies leveraging Cadence technology.
Seniority
Senior Principal, hands-on IC implementation & strategy