Group Director, Design Engineering - Front End
Core
Lead Front End Design projects and mentor RTL design engineers to define microarchitectural features for IPs and subsystems.
Role type
Senior IC Front End Design Engineer (Leadership)
Builds
Complex digital logic IPs and subsystems for semiconductor products
Domain
Semiconductor / Digital Logic Design
Deliverable
production ML models | product features (via careerplan.io/jobs/R51782-group-director-design-engineering-front-end-at-cadence)
Required skills
RTL design (Verilog, SystemVerilog, VHDL), Microarchitecture definition, Pre-silicon verification (Lint, CDC, FV), Synthesis, SDC creation, IP creation, SoC integration
Preferred skills
Cadence front end toolset experience
Responsibilities
Guide and mentor a team of RTL design engineers, Define and develop microarchitectural features for IPs and subsystems, Write, debug, and optimize RTL code, Oversee pre-silicon verification activities, Work closely with cross-functional teams including DV, PD, Architecture, and firmware engineers
Seniority
Senior, hands-on IC with leadership responsibilities
