Lead Design Engineer
Core
Develop firmware for DDR5 PHY using microcontrollers and collaborate on training algorithms for memory subsystems.
Role type
Lead Design Engineer (Firmware/Embedded)
Builds
DDR5 PHY IP front-end designs for memory subsystems
Domain
Semiconductor / High-speed Memory Interfaces
Deliverable
production ML models | product features | infrastructure
Required skills
DDR5 JEDEC spec knowledge, bare-metal firmware development, C programming for embedded systems, RTL simulation debugging, Shell/Perl/Python/TCL scripting, Verification EDA tools proficiency
Preferred skills
Experience with High-speed SerDes or Memory interface Physical Layer blocks
Technologies
C, Verilog, Microcontrollers, DDR5, RTL simulators, Waveform viewers
Responsibilities
Develop firmware for DDR5 PHY using microcontrollers, Develop low-level APIs on Microcontrollers, Collaborate with hardware designers to derive training algorithms, Collaborate with verification team on firmware-hardware co-verification, Develop and debug firmware in RTL based hardware simulations, Develop and debug on Silicon bring-up boards
Seniority
Lead, hands-on IC
