Design Engineer II
Core
Verification of digital RTL and development of reusable verification components and environments for high-performance physical IP.
Role type
Mid-level IC verification engineer (digital RTL)
Builds
Reusable verification components, environments, and test plans for industry-standard protocols
Domain
Semiconductor / Digital Verification / Physical IP
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital RTL verification, UVM, Metric Driven Verification, SystemVerilog Assertions (SVAs), Functional coverage, Code coverage, Digital design flow
Preferred skills
SystemVerilog UVM coding, Scripting (Python, Perl, Ruby, Sed, Awk), Standard protocols (PCIe, USB, SATA, Ethernet, Display Port, HDMI), Formal verification, Mixed signal design, Low power verification (CPF/UPF), Cadence tools
Technologies
SystemVerilog, UVM, Python, Perl, Ruby, Cadence tools
Responsibilities
Verify digital RTL, develop reusable verification components and environments, contribute to verification flow development, test plan development and execution, functional and code coverage closure
Seniority
Mid-level, hands-on IC
