Design Engineer II
Core
Post-Silicon Physical Layer Electrical Validation for high-speed SERDES protocols.
Role type
Mid-level IC Design Engineer (Physical Validation)
Builds
Validated electrical interfaces for high-speed data protocols
Domain
Semiconductor / Hardware Design / Electrical Engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
High-speed SERDES protocol validation, Oscilloscope usage, Network Analyzer usage, Bit Error Rate Tester (BERT) operation, FPGA prototyping, PCB schematic design, PCB layout design, Verilog RTL coding, Labview, Python, C/C++, TCL
Preferred skills
Team management, Full project validation leadership, Pre-Silicon IP/SoC validation, Board bring-up & Debug, Hiring interviews, Mentoring
Technologies
PCIe, USB, DP, Ethernet, SRIO, JESD204, DDRIO, FPGA, Labview, Python, C/C++, TCL, Verilog
Responsibilities
Conduct post-silicon electrical validation on high-speed SERDES protocols, Operate lab equipment (Oscilloscopes, Network Analyzers, BERTs), Perform FPGA design and PCB prototyping, Lead pre-silicon validation and board bring-up efforts
Seniority
Mid-level, hands-on IC