Lead Designer, Layout
Core
Execute full-custom analog and mixed-signal IC layouts from floorplan through signoff, developing parasitic-aware strategies for power stages, LDOs, references, and data converters.
Role type
Senior IC layout engineer (analog/mixed-signal)
Builds
High-performance analog and mixed-signal integrated circuits for industrial, automotive, and communications markets
Domain
Semiconductor design (analog/mixed-signal IC layout)
Required skills
Full-custom analog/mixed-signal IC layout, Cadence Virtuoso Layout Suite, physical verification (Calibre/PVS), precision matching techniques, parasitic extraction, SKILL scripting
Preferred skills
AI/ML for layout automation, Python/TCL automation, high-voltage and BCD process layout
Technologies
Cadence Virtuoso, Calibre, PVS, SKILL, Python, TCL
Responsibilities
Execute full-custom layout for analog/mixed-signal blocks including power stage FET metallization and data converters; Develop block-level and chip-level floorplans optimizing area, routing, and signal integrity; Apply precision matching techniques and noise isolation structures; Perform physical verification (DRC, LVS, ERC) and parasitic extraction; Support layout methodology improvements and junior designer development
Seniority
Senior, hands-on IC
