Senior Physical Design Engineer
Core
End-to-end physical implementation and signoff of digital blocks and SoCs, covering RTL-to-GDSII flow.
Role type
Senior Physical Design Engineer
Builds
Digital blocks and System-on-Chips (SoCs)
Domain
Semiconductor / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-GDSII implementation, floor-planning, CTS, routing, equivalence checking, timing closure, physical verification, synthesis, timing constraints, DRC, LVS, IR/EM analysis
Preferred skills
Cadence or Synopsys environment experience
Technologies
Cadence, Synopsys
Responsibilities
Execute RTL-to-GDSII implementation activities including floor-planning, CTS, routing, equivalence checking, timing closure, and physical verification; Use industry-standard physical design flows for implementation, optimization, and signoff; Analyze and resolve timing, power, IR/EM, DRC, and LVS issues
Seniority
Senior, hands-on IC
