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Senior Engineer, Analog Design Engineering

Taiwan, Taipei, Songgao💼 Full-time🗓 2026-09-16 → 2026-09-26

Core

Designing transistor-level analog/mixed-signal circuits and validating performance in the lab for consumer IC products.

Role type

Senior IC analog design engineer

Builds

Consumer IC products

Domain

Semiconductor / Analog & Mixed-Signal Design

Deliverable

production ML models | product features

Required skills

Transistor-level circuit design, AMS simulation, DC-DC topology knowledge, Cadence environment, Simplis, Verilog-A/AMS modeling, Verilog RTL reading, Test plan development, Lab validation

Preferred skills

Buck/boost/charge pump/LDO topologies, Python scripting, Shell scripting, WREAL modeling

Technologies

Cadence, Simplis, Verilog-A, Verilog-AMS, Verilog RTL, Python, Shell

Responsibilities

Create transistor level designs of circuits to meet specifications, Verify designs using transistor-level and behavioral-level simulations, Supervise circuit layout, Perform AMS simulation for top level verification, Model DC-DC switching regulator's behavior, Write circuit documentation and test plan, Validate circuit performance in the lab

Seniority

Senior, hands-on IC

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