Staff Design Verification Engineer
Core
Staff Design Verification Engineer responsible for pre-silicon verification of mixed-signal products, executing 100% verification coverage using DMS and AMS methods, and establishing best-practice verification flows.
Role type
Staff IC design verification engineer (analog/mixed-signal)
Builds
Mixed-signal analog and digital products for data center and energy applications
Domain
Semiconductor / Analog and Mixed-Signal (AMS) IC design
Deliverable
production ML models | product features
Required skills
Full chip level design verification, IC top-level DMS SV/UVM, Object-Oriented and Randomized Verification, Gate Level Simulation, Top-level metric-driven analog mixed-signal (AMS) simulations, Modelling and validation of analog blocks (RNM, Verilog-AMS), Proficiency with Cadence tool suite (Xcelium/IMC/Virtuoso), Verification planning tools (ePlanner/vManager), Scripting languages (Shell/TCL/Perl/Python), FPGA prototyping and pre-silicon validation, Experience with multiple clock and power domains
Technologies
Cadence Xcelium, Cadence IMC, Cadence Virtuoso, ePlanner, vManager, Verilog-AMS, RNM, UVM, DMS, FPGA
Responsibilities
Contribute to pre-silicon verification of mixed-signal products, Bridge verification and validation environments supporting post-silicon validation, Execute 100% verification coverage combining DMS and AMS, Establish and continuously improve verification flows, methodologies and models
Seniority
Staff, hands-on IC with mentorship and methodology definition