Principal Engineer, Digital Design Engineer (AI/ML)
Core
Lead architecture and implementation of complex digital subsystems within mixed-signal and power management ICs, driving AI/ML adoption to optimize design automation and productivity.
Role type
Principal Digital Design Engineer (AI/ML)
Builds
Next-generation mixed-signal and power management ICs (SoCs)
Domain
Semiconductor / Digital IC Design / AI/ML for EDA
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog, Python scripting, Static Timing Analysis (STA), Synthesis, DFT methodologies, Cadence Genus/Tempus/Conformal, Digital architecture definition, RTL optimization
Preferred skills
Place-and-route (Innovus), Low-power design techniques, Mixed-signal SoC integration, Clock domain crossing analysis
Technologies
Verilog, SystemVerilog, Python, Tcl, Genus, Innovus, Tempus, Conformal, Cadence
Responsibilities
Drive adoption of AI/ML methodologies to optimize synthesis, timing closure, and design space exploration; Define and lead digital architecture for complex SoCs; Lead RTL design, coding, and optimization; Own the synthesis-to-signoff flow; Lead architecture and design reviews; Influence design flows and IP reuse strategies; Collaborate with analog design teams to define digital-analog interfaces
Seniority
Principal, hands-on IC design with strategic influence
