Senior Engineer, Physical Design Engineering
Core
Senior/Lead Physical Design Engineer developing complex mixed-signal System-on-Chips (SoCs) for high-speed, leading-edge process nodes.
Role type
Senior IC physical design engineer (mixed-signal SoC)
Builds
Complex mixed-signal SoCs with multiple processor cores and high-speed signal processing hardware
Domain
Semiconductor / Mixed-signal SoC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital place and route, PnR signoff, Floor Planning, Power Plan, Clock Planning, Clock Tree Synthesis, Parasitic Extraction, Static Timing analysis, constraint development, TCL scripting, Perl scripting
Preferred skills
Device/interconnect understanding, UDSM technologies
Responsibilities
Implement complex high-speed SoC designs in cutting-edge process technologies (22nm, 16nm, 7nm), handle tapeout of complex high-speed SoC designs, innovate on flows to meet QoR targets and ensure predictability
Seniority
Senior, hands-on IC
