Staff Engineer, Design Verification Engineering
Core
Provide technical leadership in developing verification strategies for complex analog and mixed-signal designs, architecting sophisticated verification environments and ensuring product quality.
Role type
Staff Design Verification Engineer (Mixed-Signal/Analog)
Builds
Complex analog and mixed-signal semiconductor designs
Domain
Semiconductor / Analog & Mixed-Signal Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, Mixed-Signal Verification, Debugging (RTL/Gate-level), EDA Tools (Cadence/Synopsys), Python/Perl/TCL/Shell scripting
Preferred skills
MS/PhD in EE/CE, 7-10+ years in digital design verification
Technologies
SystemVerilog, UVM, Cadence, Synopsys, Python, Perl, TCL, Shell
Responsibilities
Architect and lead verification strategy for complex designs; Design and implement UVM-based verification environments; Guide and develop junior engineers; Coordinate work across organizational lines with design teams; Lead complex debugging efforts across RTL and gate-level simulations; Drive functional and code coverage closure; Lead post-silicon validation activities; Serve as principal customer contact on projects
Seniority
Staff, technical leadership & mentorship