Staff Physical Design Engineer
Core
Own end-to-end physical implementation (floorplanning, power planning, placement, CTS, routing, ECO) for complex blocks or subsystems across advanced technology nodes (e.g., 22nm, 16nm, 7nm, 5nm, 4nm) and lead a small group of engineers to achieve high-quality, on-time delivery.
Role type
Staff Physical Design Engineer (SoC)
Builds
Advanced-node System-on-Chip (SoC) physical implementations
Domain
Semiconductor / Physical Design / Digital SoC
Required skills
End-to-end physical design implementation, Timing closure, Congestion resolution, IR/EM analysis, Signal integrity, Physical verification (DRC/LVS), Hierarchical PNR strategies, IO ring/PG structures, EDA tool debugging, Flow automation, Technical leadership, Mentorship
Preferred skills
None stated
Technologies
Cadence Innovus, Synopsys ICC2, Tempus, PrimeTime, RedHawk, Voltus
Responsibilities
Drive timing closure, congestion resolution, IR/EM, and signal integrity to meet PPA targets; Define and refine hierarchical PNR strategies and integration guidelines; Develop and maintain physical design methodologies, scripts, and flows; Provide technical direction and mentor junior engineers; Collaborate with RTL, STA, DFT, and packaging teams to converge on implementation-friendly architectures.
Seniority
Staff, hands-on IC with technical leadership
