Principal Engineer, Design Verification
Core
Lead functional verification for complex ASIC/SoC designs, specifically focusing on Ethernet products to ensure standards compliance, performance, and interoperability.
Role type
Principal Verification Engineer (ASIC/SoC)
Builds
High-quality silicon for Ethernet products
Domain
Semiconductor / Hardware Verification / Networking Protocols
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, SVA, Ethernet protocol architecture, verification strategy, testbench architecture, coverage-driven verification, bug triage, emulation, FPGA prototyping
Preferred skills
Mentorship, process improvement, cross-functional collaboration
Technologies
SystemVerilog, UVM, SVA, Ethernet (MAC, PCS, PHY)
Responsibilities
Define and own verification strategy and methodology at IP, subsystem, and SoC levels; Architect scalable verification environments and reusable VIPs; Ensure first-pass silicon success through rigorous functional and protocol compliance verification; Mentor verification engineers and establish best practices; Collaborate with architecture, RTL, and software teams on standards compliance and performance assumptions.
Seniority
Principal, hands-on IC with mentorship
