Device Integration Engineer
Core
Process-device co-optimization for 2nm Gate-All-Around (GAA) transistor performance, reliability, and yield at Samsung Austin Semiconductor.
Role type
Senior individual-contributor device integration engineer
Builds
2nm GAA technology derivatives and industry-leading device performance
Domain
Semiconductor manufacturing / Advanced node device engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DOE analysis, root cause analysis, electrical test (ET) trend analysis, parametric yield management, WAT management, process integration knowledge, data mining, SPC, electrical device characterization
Preferred skills
Spotfire, SPICE modeling, Local Layout Effects (LLE) analysis, Material to Hardware Correlation (MHC)
Technologies
Spotfire, SPICE, inline metrology, FDC
Responsibilities
Perform split lot design and DOE analysis to identify key process knobs impacting device performance and yield; Lead root cause analysis for device failures and non-conformances; Own Parametric Yield and Wafer Acceptance Electrical Test (WAT) management for customer accounts; Conduct Local Layout Effects (LLE) analysis to characterize transistor performance variability in GAA nanosheet devices; Lead Material to Hardware Correlation (MHC) task force to link upstream metrology data to final electrical device performance.
Seniority
Senior, hands-on IC
