Analog Design Engineer
Core
Designing custom high-speed analog and mixed-signal circuits for SerDes-based architectures and PHY IPs.
Role type
Senior Analog Design Engineer (SerDes/PHY)
Builds
High-speed analog & mixed-signal blocks (transmitters, receivers, clocking, equalizers, serializers/deserializers) for UCIe, PCIe, and other PHY IPs.
Domain
Semiconductor, High-Speed Serial Interfaces, Advanced Process Technologies (FinFET, GAA)
Deliverable
production ML models | product features | infrastructure
Required skills
Custom analog circuit design, high-speed analog & mixed-signal design, SerDes architecture design, PHY IP development, advanced process technology design (FinFET, GAA), silicon bring-up, silicon testing/debug, team mentoring, full-chip design
Preferred skills
PAM4 architecture experience, Die-to-Die or UA Link experience, high-speed architectures (56/112/224 GbpS), silicon bring-up experience
Technologies
UCIe, PCIe, FinFET, GAA, PAM4, 56/112/224 GbpS
Responsibilities
Design custom analog circuits for SerDes based architectures, develop high-speed analog & mixed-signal blocks, mentor junior team members, work in a dynamic environment with multiple product lines
Seniority
Senior, hands-on IC