Design Verification Engineer
Core
Develop and maintain SystemVerilog/UVM verification environments for high-speed SerDes and PHY blocks, writing testbenches, functional coverage models, and assertions to verify digital and analog silicon.
Role type
Design Verification Engineer (SerDes/PHY)
Builds
High-speed SerDes IP for PCIe, Ethernet, and other industry-standard interfaces
Domain
Semiconductor / FPGA / Digital & Analog Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM concepts, digital design fundamentals (synchronous logic, FSMs, pipelining, clock domain crossing), simulation and debugging, RTL analysis
Preferred skills
Experience with high-speed silicon verification, firmware-hardware co-verification
Technologies
SystemVerilog, UVM, SerDes, PHY, PCIe, Ethernet
Responsibilities
Develop and maintain verification environments for SerDes and PHY blocks, write testbenches and functional coverage models, run simulations and debug RTL/testbench issues, collaborate with design and analog teams on block-level and top-level verification
Seniority
Early-career, hands-on IC
