Senior Digital ASIC Design Engineer
Core
Design and integration of next-generation ASIC technologies for high-performance optical networking solutions.
Role type
Senior Digital ASIC Design Engineer
Builds
Scalable silicon solutions for WaveLogic products powering critical telecommunications infrastructure
Domain
Telecommunications / Semiconductor / Optical Networking
Deliverable
production ML models | product features | infrastructure
Required skills
Verilog, SystemVerilog, Python, digital design concepts, synthesis, static timing analysis (STA), timing closure, asynchronous clock domain crossing
Preferred skills
C, C++, SystemC, scripting, object-oriented programming, ASIC verification
Technologies
WaveLogic products, advanced semiconductor nodes
Responsibilities
Contribute to top-level ASIC design and integration; Interpret architecture and functional specifications; Develop and assemble top-level RTL designs; Maintain and enhance technology-specific libraries; Own and manage tool flows for ASIC integration; Create timing constraints and analyze backend reports; Perform lab validation of ASIC prototypes
Seniority
Senior, hands-on IC