FPGA Development Tools Engineer
Core
Senior Technical Lead driving development, modeling, and validation of FPGA IP and simulation models within the Altera Quartus Prime ecosystem.
Role type
Senior Technical Lead, FPGA IP & Simulation
Builds
FPGA IP blocks, high-fidelity simulation models (behavioral, cycle-accurate), verification environments
Domain
Semiconductor / FPGA Design / Digital Logic
Deliverable
production ML models | product features
Required skills
RTL design (Verilog/SystemVerilog/VHDL), FPGA IP development, simulation & verification, SystemVerilog assertion-based verification, Quartus Prime toolchain, complex debugging, technical leadership, automation frameworks (Python, Tcl)
Preferred skills
AI-assisted workflows, regression infrastructure design, mentorship
Technologies
Altera Quartus Prime, SystemVerilog, VHDL, Python, Tcl
Responsibilities
Define technical direction for IP and simulation models; Lead design reviews, architecture discussions, and validation strategies; Design and implement FPGA IP and high-fidelity simulation models; Define and enforce robust verification methodologies; Lead debugging of complex issues across simulation, fitter, and timing analysis; Champion engineering productivity improvements via automation frameworks
Seniority
Senior, hands-on IC with leadership
