Physical Design Engineer/STA
Core
Performs physical design implementation of custom IP and SoC designs from RTL to GDS, conducting verification and signoff to create manufacturing-ready design databases.
Role type
Physical Design Engineer / Static Timing Analysis (STA) Engineer
Builds
Custom IP and System-on-Chip (SoC) designs
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (GDS design databases)
Required skills
RTL to GDS flow, synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability analysis, power and noise analysis, formal equivalence verification, layout verification, electrical rule checking, structural design checking, physical clock design, timing closure, coverage analysis, multiple power domain analysis, DFT, EDA tools
Preferred skills
physical design methodologies, flow automation
Technologies
industry standard EDA tools
Responsibilities
Conduct physical design flow (synthesis, place and route, CTS, floor planning, STA, power/noise analysis), perform verification and signoff (formal equivalence, timing, power integrity, ERC, DRC), analyze results and recommend fixes for violations, optimize designs for power/frequency/area, develop and improve physical design methodologies and flow automation
