Memory System Designer and Place and Route Engineer
Core
Architect and design large memory blocks and subsystems, implementing RTL and performing physical design (place and route) to ensure design closure.
Role type
Senior IC memory system designer and place-and-route engineer
Builds
Large memory blocks and subsystems
Domain
Semiconductor / Memory
Required skills
Verilog RTL design, Place and route, Static Timing Analysis (STA), Design Rule Check (DRC), Electromigration/IR drop analysis, Python scripting, Synthesis tools, Logical equivalency checking, Memory behavior understanding
Preferred skills
Automation script writing, Tool proficiency
Responsibilities
Architect memory subsystems, Implement RTL designs, Perform place and route, Achieve design closure (timing, DRC, LVS, EM/IR), Run synthesis and debug netlists
Seniority
Senior, hands-on IC
