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IC Verification Engineer

USA-California-San Jose-1320 Ridder Park Drive💼 Full-time💰 $121,900–$121,900🗓 2026-09-21 → 2026-09-25

Core

Develop test plans, functional coverage, and scalable test benches for Block/Core/SOC features to verify complex protocols.

Role type

IC Verification Engineer

Builds

Verification environments and testbenches for semiconductor blocks, cores, and System-on-Chip (SoC) designs

Domain

Semiconductor hardware verification

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification environments)

Required skills

System Verilog, UVM/VMM/OVM verification methodologies, Object-Oriented Programming, complex protocol analysis (PCIe), test plan architecture, functional coverage modeling, regression debugging

Preferred skills

PCIe protocol expertise

Technologies

System Verilog, UVM, VMM, OVM

Responsibilities

Develop test plans and functional coverage for Block/Core/SOC features; Architect and develop scalable, re-usable test benches; Build pseudo-random tests to achieve full functional coverage; Debug regression failures and analyze coverage gaps; Lead documentation of verification strategy and conduct reviews with design/architecture teams; Drive improvements in verification quality and efficiency

Seniority

Senior, hands-on IC

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