R&D Engineer IC Design 5
Core
Developing complex verification environments and test plans for high-performance network switch ASICs and FPGAs.
Role type
Senior IC ASIC system-level verification engineer
Builds
High-performance network switch ASICs and FPGAs
Domain
Networking hardware (ASIC/FPGA)
Deliverable
production ML models | product features
Required skills
Verilog, SystemVerilog, UVM, C/C++, object-oriented programming (OOP), ASIC design flows, deep sub-micron technologies
Preferred skills
Networking protocols (Ethernet, PCIe, routing/switching), networking background
Technologies
UVM, SystemVerilog, Verilog
Responsibilities
Develop complex verification environments, create comprehensive test plans, verify high-performance network switch ASICs/FPGAs, collaborate with system architects and design engineers, architect testbenches
Seniority
Senior, hands-on IC
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