IO and Mixed Signal Layout Design Engineer
Core
Design full custom layouts of I/O libraries and Analog Mixed Signal IP in planar and FinFET technologies, driving floor-planning and verification to meet performance metrics.
Role type
Senior IC analog/mixed-signal layout engineer
Builds
I/O libraries and Analog Mixed Signal IP blocks
Domain
Semiconductor physical design (analog/mixed-signal)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
I/O library design, Analog Mixed Signal IP development, Planar and FinFET layout, Full-chip concepts, ESD and Latch-up principles, Cadence Virtuoso, Siemens CALIBRE, DRC/LVS/ANT/ERC/DFM verification, Physical Design flow (LEF/PnR)
Preferred skills
AI/automation in layout, Script Programming, SKILL Programming
Responsibilities
Design full custom layouts of I/O libraries and Analog Mixed Signal IP's; Drive critical floor-planning decisions; Perform comprehensive layout verification; Complete ownership from end to end deliverables
Seniority
Senior, hands-on IC