R&D Engineer
Core
R&D Engineer responsible for physical design, verification, and tapeout of analog/RF ICs, including place & route, CTS, DRC/LVS, and timing fixes.
Role type
Senior IC physical design engineer (analog/RF)
Builds
Production ASICs and RF chips
Domain
Semiconductor / VLSI / Analog & RF
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Place & Route, CTS, DRC, LVS, Antenna, LUP, Analog block integration, RC requirement analysis, Calibre rule deck, Perl scripting, TCL scripting, VLSI fabrication process knowledge, Timing ECOs, IR drop fixes, SPEF extraction, Signal EM fixes, Noise analysis
Preferred skills
Cadence Innovus, Cadence Calibre, STA, PTSI
Technologies
Cadence Innovus, Calibre, Perl, TCL
Responsibilities
Perform place and route, CTS, and routability analysis; Execute physical verification (DRC, LVS, Antenna, LUP); Integrate analog blocks and meet RC requirements; Implement timing ECOs, IR drop fixes, SPEF extraction, and signal EM fixes; Conduct integrity checks and manage post-tapeout eJob view release.
Seniority
Mid-to-Senior, hands-on IC
