IC Design Engineer
Core
Perform static and dynamic sign-off, power estimation, and signal/power EM analysis at block and full-chip levels for SoC designs.
Role type
IC Design Engineer (Physical Design/Power Integrity)
Builds
Static and dynamic sign-off deliverables, power grids, and system-level power distribution network (PDN) analyses for SoCs.
Domain
Semiconductor / IC Physical Design / Power Integrity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static IR sign-off, Dynamic IVD analysis, Power estimation (vector/vectorless), Signal/Power EM analysis, Custom power grid implementation, System-level PDN analysis, Bump assignment, Package routing optimization, Mixed-mode analysis, PG Grid resistance checks
Preferred skills
SoC architecture knowledge, Packaging integration experience
Technologies
Static IR tools, Dynamic IVD tools, EM analysis tools, Power grid design tools, PDN analysis tools
Responsibilities
Conduct block and full-chip static IR and dynamic IVD sign-off; Perform power estimation on blocks and full chip using vector and vectorless methods; Execute signal and power EM sign-off at block and full-chip levels; Implement custom power grids for blocks and hardmacs; Perform system-level PDN analysis covering board, package, interposer, and die; Collaborate with SoC and packaging teams on bump assignment and package routing optimization; Conduct dynamic analysis using vectorless, vectors, and mixed-mode techniques; Perform PG grid resistance checks.
