IC Verification Engineer
Core
Architect and develop scalable, reusable testbench environments and drive test plans to achieve full functional coverage for Block/Core/SOC features.
Role type
Senior IC verification engineer (ASIC)
Builds
Verification environments, test plans, pseudo-random tests, and functional coverage models for complex SoC designs.
Domain
Semiconductor hardware design and verification (ASIC)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM/VMM, functional coverage methodology, pseudo-random test generation, regression debugging, complex protocol analysis (PCI Express), ASIC full cycle experience, mentorship
Preferred skills
PCIe protocol expertise, Python/Perl scripting, Makefiles, AXI protocol verification
Technologies
System Verilog, UVM, VMM, PCIe, AXI, Python, Perl, Makefiles
Responsibilities
Architect scalable testbench environments, drive test plans for Block/Core/SOC, build pseudo-random tests for functional coverage, debug regression failures, mentor junior engineers, lead verification strategy documentation and reviews.
Seniority
Senior, hands-on IC
