Senior Digital VLSI Design Engineer
Core
Technical authority responsible for defining and enforcing synchronization strategies, constraint creation, and sign-off for high-speed complex IPs in advanced process nodes.
Role type
Senior Digital VLSI Design Engineer (Synthesis, DFT, CDC/RDC)
Builds
High-speed complex IPs for SOC teams
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Synthesis, DFT, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), constraint creation, structural verification, functional verification, RTL design review, testability analysis
Preferred skills
High-speed interface design (SerDes, LPDDR5/6, DDR4/5, HBM), automated flow development, mentorship
Technologies
SpyGlass CDC/RDC, SpyGlass Lint, JasperGold, Meridian
Responsibilities
Define and enforce synchronization strategies across multi-clock domains, own constraint creation for synthesis and full-chip CDC/RDC methodology, collaborate with Architecture and Chip Lead teams on testability and clocking architectures, identify metastability or reset-glitch issues before RTL freeze, mentor the design team on best practices
Seniority
Senior, hands-on IC