Design Engineer
Core
Architect block-level design specifications and implement efficient RTL designs for next-generation Ethernet Switching ASICs and security protocols.
Role type
Senior Front End Logic Design Engineer (RTL/micro-architect)
Builds
Networking and security ASICs for AI & DC infrastructure
Domain
Semiconductor / High-Speed Digital Design
Deliverable
production ML models | product features
Required skills
RTL coding (Verilog/System-Verilog), Logic Synthesis, Timing/Area/Power optimization, HDL scripting (Perl/TCL/Python), Ethernet L2/L3/L4 protocols, High-speed digital design (1Ghz+)
Preferred skills
Security protocols/algorithms, Area/power estimation methods, Code Assist tools
Responsibilities
Architect block level design specifications from system/marketing requirements, Efficient design implementation for different components of networking ASICs, RTL coding, Lint & CDC checks, Logic Synthesis and driving Timing/Area/Power optimizations, Support pre & post silicon verification activities, Support external teams for IP integration and physical implementation
Seniority
Senior, hands-on IC
