Post silicon validation engineer
Core
Drive bring-up, characterization, and debugging of next-generation Ethernet and PCIe Retimer chips, focusing on advanced Ethernet physical layer (PHY) validation.
Role type
Post-silicon validation engineer (high-speed networking)
Builds
Production Ethernet and PCIe Retimer ICs
Domain
Networking hardware (Ethernet/PCIe) and silicon validation
Deliverable
production ML models | product features
Required skills
Ethernet PHY architecture, PAM4/NRZ signaling, FEC, Auto-Negotiation, Link Training, high-bandwidth oscilloscopes, BERTs, Ethernet traffic generators, PCIe analyzers, Python scripting, C/C++ programming
Preferred skills
ARM-based microcontroller experience, GPIO/MDIO/I2C protocols, protocol analyzer usage
Technologies
Python, C, C++, Ixia, Spirent
Responsibilities
Hands-on bring-up of multi-rate Retimer ICs, Validate Ethernet (100G/400G/800G) and PCIe (Gen 5/6) for IEEE and PCI-SIG compliance, Build Python-based automated test frameworks for Ethernet throughput, BER, and control path testing, Root-cause complex silicon, link training, and firmware bugs using protocol analyzers and traffic generators
Seniority
Senior, hands-on IC